The present invention relates to a processor having a data-dependent clock gating function.
Clock gating technique for stopping the supply of a clock signal to a circuit block in a processor when it is not necessary to operate the circuit block is known. In accordance with this technique, the power consumption of a processor can be reduced.
An image processing apparatus disclosed in Japanese Laid-Open Publication No. 8-65496 includes two circuit blocks. In each of a plurality of operation modes of the apparatus, the supply of a clock signal to at least one of the two circuit blocks is stopped. An operation mode signal, supplied from the outside of the image processing apparatus, specifies in which mode the apparatus should operate.
A microcomputer disclosed in Japanese Laid-Open Publication No. 5-324871 includes a central processing unit (CPU) and a plurality of peripheral hardware devices. Each of the peripheral hardware devices incorporates a core section and a clock controller. Each clock controller allows the supply of a clock signal to the associated core portion thereof only within a predetermined time zone between a time when the peripheral hardware device is selected by the CPU and a time determined by a timer.
A video encoder operating in compliance with an MPEG (Moving Picture Experts Group) standard includes a large number of operation units for motion prediction, DCT (discrete cosine transform), quantization, variable length coding and the like. It is known that the processing time of each such operation unit is dependent on image data. However, neither the conventional image processing apparatus nor the conventional microcomputer could perform data-dependent clock gating.